Project Statistics |
PROPEXT_xilxBitgCfg_Rate_virtex7=22 |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Timing Performance |
PROP_LastAppliedStrategy=SmartXplorer - maplogicoptregdup;E:/mat/SKY_PCIE/ak7_map_ges/ISE_t28_core_100_141/maplogicoptregdup.xds |
PROP_ManualCompileOrderImp=false |
PROP_MapLogicOptimization_virtex5=true |
PROP_MapPlacerCostTable_virtex5=2 |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=Modelsim-PE VHDL |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=E:/mat/SKY_PCIE/ak7_map_ges/ISE_t28_core_100_141/maplogicoptregdup.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_bitg_SetSPIConfigBusWidth=4 |
PROP_intProjectCreationTimestamp=2012-06-27T19:24:50 |
PROP_intWbtProjectID=CD3048388ACD4377926B999338429CD3 |
PROP_intWbtProjectIteration=17 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxNgdbldMacro=changed |
PROP_xilxNgdbld_AUL=true |
PROP_xstNetlistHierarchy=Rebuilt |
PROP_AutoTop=true |
PROP_DevFamily=Kintex7 |
PROP_MapExtraEffort_virtex5=Normal |
PROP_MapRegDuplication_virtex5=On |
PROP_ibiswriterOutputFile=SKY_PCIE_AK7 |
PROPEXT_xilxPARextraEffortLevel_virtex5=Normal |
PROP_DevDevice=xc7k325t |
PROP_DevFamilyPMName=kintex7 |
PROP_DevPackage=ffg900 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=VHDL |
PROP_netgenPostMapSimModelName=SKY_PCIE_AK7_map.vhd |
PROP_netgenPostParSimModelName=SKY_PCIE_AK7_timesim.vhd |
PROP_netgenPostSynthesisSimModelName=SKY_PCIE_AK7_synthesis.vhd |
PROP_netgenPostXlateSimModelName=SKY_PCIE_AK7_translate.vhd |
PROP_netgenRenameTopLevEntTo=SKY_PCIE_AK7 |
FILE_UCF=1 |
FILE_VERILOG=76 |
FILE_VHDL=25 |