SKY_PCIE_KC705 Project Status (08/08/2012 - 23:52:02)
Project File: iSKY_PCIe_KC705.xise Parser Errors:
Module Name: SKY_PCIE_KC705 Implementation State: Programming File Generated
Target Device: xc7k325t-2ffg900
  • Errors:
No Errors
Product Version:ISE 14.1
  • Warnings:
8570 Warnings (8565 new)
Design Goal: Timing Performance
  • Routing Results:
All Signals Completely Routed
Design Strategy: SmartXplorer - maplogicoptregdup
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 21,776 407,600 5%  
    Number used as Flip Flops 21,776      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 16,539 203,800 8%  
    Number used as logic 12,394 203,800 6%  
        Number using O6 output only 7,029      
        Number using O5 output only 288      
        Number using O5 and O6 5,077      
        Number used as ROM 0      
    Number used as Memory 1,871 64,000 2%  
        Number used as Dual Port RAM 1,772      
            Number using O6 output only 92      
            Number using O5 output only 30      
            Number using O5 and O6 1,650      
        Number used as Single Port RAM 0      
        Number used as Shift Register 99      
            Number using O6 output only 99      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 2,274      
        Number with same-slice register load 2,234      
        Number with same-slice carry load 40      
        Number with other load 0      
Number of occupied Slices 7,003 50,950 13%  
Number of LUT Flip Flop pairs used 22,546      
    Number with an unused Flip Flop 5,536 22,546 24%  
    Number with an unused LUT 6,007 22,546 26%  
    Number of fully used LUT-FF pairs 11,003 22,546 48%  
    Number of unique control sets 867      
    Number of slice register sites lost
        to control set restrictions
4,551 407,600 1%  
Number of bonded IOBs 138 500 27%  
    Number of LOCed IOBs 138 138 100%  
    IOB Flip Flops 17      
    IOB Master Pads 9      
    IOB Slave Pads 9      
    Number of bonded IPADs 18      
    Number of bonded OPADs 16      
Number of RAMB36E1/FIFO36E1s 32 445 7%  
    Number using RAMB36E1 only 32      
    Number using FIFO36E1 only 0      
Number of RAMB18E1/FIFO18E1s 8 890 1%  
    Number using RAMB18E1 only 8      
    Number using FIFO18E1 only 0      
Number of BUFG/BUFGCTRLs 7 32 21%  
    Number used as BUFGs 6      
    Number used as BUFGCTRLs 1      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 64 500 12%  
    Number used as IDELAYE2s 64      
    Number used as IDELAYE2_FINEDELAYs 0      
Number of ILOGICE2/ILOGICE3/ISERDESE2s 64 500 12%  
    Number used as ILOGICE2s 0      
Number used as    ILOGICE3s 0      
    Number used as ISERDESE2s 64      
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0 150 0%  
Number of OLOGICE2/OLOGICE3/OSERDESE2s 112 500 22%  
    Number used as OLOGICE2s 9      
    Number used as OLOGICE3s 0      
    Number used as OSERDESE2s 103      
Number of PHASER_IN/PHASER_IN_PHYs 8 40 20%  
    Number used as PHASER_INs 0      
    Number used as PHASER_IN_PHYs 8      
        Number of LOCed PHASER_IN_PHYs 8 8 100%  
Number of PHASER_OUT/PHASER_OUT_PHYs 11 40 27%  
    Number used as PHASER_OUTs 0      
    Number used as PHASER_OUT_PHYs 11      
        Number of LOCed PHASER_OUT_PHYs 11 11 100%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 168 0%  
Number of BUFRs 0 40 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 840 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of GTXE2_CHANNELs 8 16 50%  
    Number of LOCed GTXE2_CHANNELs 8 8 100%  
Number of GTXE2_COMMONs 2 4 50%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 2 10 20%  
Number of IN_FIFOs 8 40 20%  
    Number of LOCed IN_FIFOs 8 8 100%  
Number of MMCME2_ADVs 2 10 20%  
Number of OUT_FIFOs 11 40 27%  
    Number of LOCed OUT_FIFOs 11 11 100%  
Number of PCIE_2_1s 1 1 100%  
    Number of LOCed PCIE_2_1s 1 1 100%  
Number of PHASER_REFs 3 10 30%  
    Number of LOCed PHASER_REFs 3 3 100%  
Number of PHY_CONTROLs 3 10 30%  
    Number of LOCed PHY_CONTROLs 3 3 100%  
Number of PLLE2_ADVs 1 10 10%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.98      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent水 8 8 23:36:32 201207115 Warnings (7115 new)694 Infos (694 new)
Translation ReportCurrent水 8 8 23:37:28 201205 Warnings (0 new)45 Infos (45 new)
Map ReportCurrent水 8 8 23:46:11 20120480 Warnings (480 new)5 Infos (5 new)
Place and Route ReportCurrent水 8 8 23:49:01 20120491 Warnings (491 new)1 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrent水 8 8 23:49:47 2012004 Infos (4 new)
Bitgen ReportCurrent水 8 8 23:51:39 20120479 Warnings (479 new)1 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportCurrent水 8 8 23:46:11 2012
WebTalk ReportCurrent水 8 8 23:51:39 2012
WebTalk Log FileCurrent水 8 8 23:51:59 2012

Date Generated: 08/08/2012 - 23:52:02